This present invention relates to power amplifiers and is more particularly directed to pulsed RF power amplifiers of the type in which several FET's or other amplifying devices are ganged together to amplify an RF input signal. The invention is more specifically directed to a technique of controlling the bias levels of the amplifying device so that they are kept at a desired operating point in their active regions.
Transistors or other amplifying device have an active region in which there is a linear relationship between gate or grid voltage and drain or plate current. For example, in a linear Class A amplifier, a bias level is selected so that when a null signal is applied to the grid, gate or other control electrode, the output current is at a desired quiescent level in about the center of the linear part of the device's active region. Because operating characteristics such as threshold voltage, transconductance etc. of the amplifying device will change, due to aging, temperature drift, or other reasons, bias control techniques have been used to maintain a reasonably constant bias current in the transistors or other device used in the gain stages of an RF power amplifier. One proposed bias control technique for an RF amplifier is described in Erb et al. U.S. Pat. No. 4,924,191.
Low-power amplifiers can include a source degeneration resistor in series with the source-drain path, and a simple biasing network on the gate to provide a stable bias current. However, high-power devices tend to have much smaller gains than low-power devices, and this requires an increased size and operating cost for network gain control techniques for high-power devices. Resistors in the source-drain path affect gain and create an output power loss, even if bypassed by a capacitor for high frequencies. This is unacceptable in high power amplifiers where any power loss will result in the need for additional power stages or an increased number of paralleled devices.
If the high-power amplifier is operated continuously, it can employ a technique that measures drain current and adjusts the gate voltage so as to keep constant the dc component of the drain current.
However, for many applications it is necessary for the amplifier to be designed for pulsed operation. In that case a static feedback network is not feasible to maintain a constant bias. This results because there is no current output flowing when the amplifier is gated off, so no bias measurement can be taken between pulses.
A previously-proposed solution to this problem involves gating each amplifying device in turn while applying a null or zero input. The bias current for each device is measured, and the results of this measurement are supplied to a processor that controls the respective bias levels. This technique requires a test mode, in which the amplifying elements are forward biased and a null input signal is applied. However, there is no provision for creating a null region for each occurrence of a pulsed input signal. Also, if the amplifier is to be operated in a continuous mode, the technique requires that a forced idle condition be imposed in turn on the amplifying elements. Thus, the effect is that the amplifier will not operate in a continuous mode.
This technique also has drawbacks in that it interferes with its user because of its forced idle condition. Additionally the feedback correction in this technique is extremely slow, and cannot prevent failure from thermal runaway for many types of transistors that require continuous, real-time feedback.
The usual technique to control bias compensation is to employ a temperature compensation network. This only corrects for thermal drift of the FET gate-to-drain threshold voltages. This does have the advantage of operating whether the amplifier is used continuously or intermittently. However, because of its open-loop nature, this technique does suffer certain drawbacks. Each FET or other device requires adjustment to set the initial bias to the required level. This most often involves a potentiometer that is set by hand. Also, the thermal drift characteristic of each FET has to match, or an adjustment has to be made during manufacture to compensate for variance in thermal drift.
Recently some circuit designers have begun to consider high power FETs for use in power amplifiers as a means to reduce cost and size of the amplifier. These FETs, which are more frequently employed in switching power supplies, have a much more abrupt gate-voltage-to-drain-current characteristic than an RF power FET. This makes a simple thermal compensation scheme difficult and costly to implement. These low-cost FETs are also very sensitive to thermal variations, which can cause thermal runaway. If this sensitivity is not addressed adequately, destruction of the device can result. That is, threshold voltage change because of temperature change is a serious problem. The fact that the gate voltage to drain current characteristic is steeper and more abrupt as compared with other transistors results in a faster and more extreme thermal runaway.